The present invention relates generally to the field of integrated circuits, and more particularly to write-bitline control in multicore static random access memory arrays.
Current implementations of Static Random Access Memory (“SRAM”) usually include a Negative Bitline Assist (“NBA”), also known as a “write assist”, circuit to ensure that negative voltages are transmitted through to all cells of the memory array. At the same time, SRAMs have been introduced that use multiple cores, only one of which may be written at a time. Engineers continue to face challenges in write-bitline circuitry for SRAM arrays involving multiple cores, NBA, or both.